In this paper, a static task scheduling and mapping heuristic approach to optimize execution time, reliability, power and temperature of multiprocessor systems on chip is presented. This method is proposed based on the list scheduling approach and utilized task replicat
More
In this paper, a static task scheduling and mapping heuristic approach to optimize execution time, reliability, power and temperature of multiprocessor systems on chip is presented. This method is proposed based on the list scheduling approach and utilized task replication, dynamic voltage and frequency scaling, and adding cooling slacks to improve reliability, power consumption and temperature to expand the design space and explore the solution set more efficiently. Due to the existing trade-offs among the considered parameters and their optimization, the optimization process is complicated and our proposed method is used the Pareto front generation technique. Moreover, our proposed method, models the objectives comprehensively to consider their dependency. Several experiments are performed to demonstrate the performance and capability of the proposed method in joint optimization of the parameters and extracting the proper solution set. Compared to the previous research, our proposed method outperforms them in optimizing the considered design parameters and its results is 19% better averagely than an efficient studied heuristic method.
Manuscript profile
